ZSZaid Saifan
Résumé

Projects / FPGA Sequence Detector

Western University · Digital logic

FPGA Sequence Detector and Logic Optimization

An 8-state Moore machine that finds a 4-bit pattern in a serial stream, then an optimization pass that made it 24% cheaper in hardware.

My roleFSM design, encoding, optimization, simulation
  • Quartus Prime
  • FPGA
  • Moore FSM
  • K-maps
S0000S1001S2011S3010S4110S5111S6101S7100one bit flipsper transitionGATE INPUT COSTBinary · 83Gray · 63−24%same behaviour, less hardware
Fig. 0State ring with Gray-coded assignments, and the gate input cost before and after.

DesignThe machine

A Moore machine with 8 states, built from D flip-flops, that detects a 4-bit sequence anywhere in a continuous stream. When a partial match breaks, the machine falls back to the state for the suffix it has already seen instead of resetting to zero.

OptimizationCheaper in gates

  • A custom Gray-code state assignment changes only one state bit per transition, which reduces the terms each next-state equation has to cover.
  • Karnaugh-map simplification took total gate input cost from 83 to 63, a 24% cut with no change in behaviour.

SimulationVerification

I checked timing and state transitions in Quartus Prime simulation, covering partial matches, broken matches and back-to-back detections as well as the normal case.

ValidationResults

83 → 63gate input cost
−24%hardware cost, same behaviour
8Moore states

05Contact

Let's build something.

I'm looking for 12–16 month co-op and internship terms starting May 2027 in power and electrical design, controls, robotics, embedded systems or hardware test.

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